The present invention relates to a semiconductor design technology and, more particularly to a clock synchronization circuit and a method for operating the same.
Generally, in a semiconductor memory device including a DDR SDRAM (Double Data Rate Synchronous DRAM), internal clock signals are produced using an external clock signal and these internal clock signals are used as reference clock signals for synchronization with various operation timing. Accordingly, a clock synchronization circuit for synchronizing the external clock signal and the internal clock signals is provided in the semiconductor memory device. A typical clock synchronization circuit is a phase-locked loop (PLL).
When the internal clock signals are produced by the phase-locked loop, a voltage controlled oscillator (VCO) is required and this voltage controlled oscillator can be classified into an analog-based operating oscillator and a digital-based operating oscillator.
FIG. 1 is a block diagram illustrating a conventional analog PLL. As shown in FIG. 1, the analog PLL includes a phase/frequency detector 110, a charge pumping device 130, a control voltage signal generator 150 and a voltage controlled oscillator (VCO) 170.
The phase/frequency detector 110 produces an up-detection signal DET_UP and a down-detection signal DET_DN which correspond to a phase/frequency difference between a reference clock signal CLK_REF and a feedback clock signal CLK_FED. The reference clock signal CLK_REF corresponds to the external clock signal and the up-detection signal DET_UP and the down-detection signal DET_DN are pulse signals which are activated according to the phase/frequency relationship between the reference clock signal CLK_REF and the feedback clock signal CLK_FED. These pulse signals will be described in relation to the corresponding operations.
The charge pumping device 130 performs positive charge pumping in response to the up-detection signal DET_UP, and negative charge pumping in response to the down-detection signal DET_DN. That is, the charge pumping device 130 supplies charge to the control voltage signal generator 150 in response to the up-detection signal DET_UP and discharges the control voltage signal generator 150 in response to the down-detection signal DET_DN.
The control voltage signal generator 150 produces an oscillation control voltage signal V_CTR through a charge operation based on the positive charge pumping operation of the charge pumping device 130, and produces the oscillation control voltage signal V_CTR through a discharge operation based the negative charge pumping operation of the charge pumping device 130. In other words, the voltage level of the oscillation control voltage signal V_CTR is dependent upon the charge and discharge operation of the charge pumping device 130. The control voltage signal generator 150 is represented having a resistance R and a capacitance C in series with a supply voltage VSS.
The voltage controlled oscillator 170 produces a PLL clock signal CLK_PLL having a frequency which corresponds to the oscillation control voltage signal V_CTR. The voltage controlled oscillator 170 may be designed to include a plurality of delay cells (not shown) as an oscillator, which feeds back differential input signals delayed by a delay time corresponding to the oscillation control voltage signal V_CTR. The generated PLL clock signal CLK_PLL becomes the feedback clock signal CLK_FED, which is inputted to the phase/frequency detector 110, and the phase/frequency detector 110 repeatedly produces the up-detection signal DET_UP and the down-detection signal DET_DN which correspond to a phase/frequency difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FED.
The phase/frequency detector 110, the charge pumping device 130, the control voltage signal generator 150 and the voltage controlled oscillator 170 form the phase-locked loop circuit, are well known to those skilled in the art, so that their detailed description will be omitted.
The operation of the phase-locked loop will be described briefly below.
The phase/frequency detector 110 produces the up-detection signal DET_UP and the down-detection signal DET_DN by detecting the phase/frequency difference between the reference clock signal CLK_REF and the feedback clock signal CLK_FED. The up-detection signal DET_UP is a pulse signal having a pulse width corresponding to the phase difference when the phase of the feedback clock signal CLK_FED lags behind that of the reference clock signal CLK_REF. The down-detection signal DET_DN is a pulse signal having a pulse width corresponding to the phase difference when the phase of the feedback clock signal CLK_FED leads that of the reference clock signal CLK_REF.
The charge pumping device 130 charges or discharges the control voltage signal generator 150 through a charge pumping operation, which is conducted by the up-detection signal DET_UP and the down-detection signal DET_DNP. Through the charging or discharging operation, the voltage level of the oscillation control voltage signal V_CTR generated by the control voltage signal generator 150 is varied. In other words, the voltage level of the oscillation control voltage signal V_CTR is raised in response to the up-detection signal DET_UP and lowered in response to the down-detection signal DET_DN.
The voltage controlled oscillator 170 produces the PLL clock signal CLK_PLL of low frequency according to the oscillation control voltage signal V_CTR of a high voltage level and also produces the PLL clock signal CLK_PLL of high frequency according to the oscillation control voltage signal V_CTR of a low voltage level. The relationship between the oscillation control voltage signal V_CTR and the PLL clock signal CLK_PLL can be changed by a design architecture. That is, it is possible to produce the PLL clock signal CLK_PLL of a low frequency according to the oscillation control voltage signal V_CTR of a low voltage level or produce the PLL clock signal CLK_PLL of high frequency according to the oscillation control voltage signal V_CTR of a high voltage level.
The feedback signal CLK_FED is the PLL clock signal CLK_PLL which is fed back to the phase/frequency detector 110. The phase/frequency detector 110 detects again a phase/frequency difference between the frequency-changed feedback clock signal CLK_FED and the reference clock signal CLK_REF.
Through these repeated detections, the phase-locked loop outputs the PLL clock signal CLK_PLL which is synchronized with the reference clock signal CLK_REF. The synchronization between the reference clock signal CLK_REF and the PLL clock signal CLK_PLL is called “phase/frequency locking.”
Meanwhile, recently, in order to increase the operation speed of the semiconductor device, the frequency of the external clock signal has repeatedly increased, up to as high as a few GHz. Jitter, which is mixed with the external clock signal and inputted to the internal circuit, cannot be disregarded in high frequency operation. Accordingly, the phase-locked loop is designed to output the PLL clock signal CLK_PLL with low jitter by improving filtering as well as by improving phase/frequency locking.
FIG. 2 is a graph showing characteristics of a jitter transfer function of the phase-locked loop of FIG. 1.
Referring to FIG. 2, the dotted line “A” shows a jitter transfer function of an ideal low pass filter, and the solid line “B” shows a jitter transfer function of a conventional low pass filter. In the phase-locked loop, the high frequency jitter component is filtered away by the low pass filter so that any high frequency jitter component is not shown in the PLL clock signal CLK_PLL to be outputted from the voltage controlled oscillator 170. However, as shown in the graph, the jitter is further amplified in the range of the bandwidth. This jitter peaking phenomenon seriously worsens the jitter of the PLL clock signal CLK_PLL by amplifying jitter caused by power noise as well as the input jitter.
The reason that the jitter peaking phenomenon is caused is that the phase-locked loop, which is a closed-loop system having two poles in the frequency domain (s-domain), does not secure a desired phase margin in the phase/frequency locking process.
Here, the pole is a value which makes a denominator of a transfer function “0”. “Zero” is an opposite concept of the pole to make a numerator of the transfer function “0”. “Zero” and “pole” are factors to determine the phase margin and are indexes to measure the stability or instability of the system.
If the phase margin is 60° in a system, the time for a signal oscillating in a time-domain to come back to a steady state can be minimized. For example, the response time may be fast when the phase margin of such a system is smaller than 60°; however, it will take the signal a lot of time to come back to the steady state because of the high instability of the signal. On the contrary, if the phase margin of the system is larger than 60°, the stability can be improved; however, the response time is slow so that it will take the signal a lot of time to come back to the steady state.
On the other hand, the phase-locked loop makes it possible to take a desired phase margin by obtaining a “zero” through control of the resistance and capacitance in the control voltage signal generator 150. However, for the following reasons it is still difficult to design a phase-locked loop which has a desired phase margin.
First, as mentioned above, a typical phase-locked loop is a closed-loop system having two poles. Therefore, since the phase margin is small and the jitter peaking phenomenon occurs, the signal jitter included in the signal is amplified and the power noise also largely amplifies the jitter. As a result, the PLL clock signal CLK_PLL deteriorates seriously.
To overcome this problem, the phase margin of the phase-locked loop can be widened by having a large resistance value of the resistor R (creating a “zero”). However, there is another problem in that the pattern jitter, which is periodically generated, is increased because of the ripple of the oscillation control voltage signal V_CTR.
That is, in the phase-locked loop, there is a problem that the pattern jitter of the oscillation control voltage signal V_CTR is largely caused when the resistance value of the resistor R is increased to remove the jitter peaking phenomenon, and there is another problem that the jitter peaking phenomenon is also caused when the resistance value of the resistor R is decreased to remove the pattern jitter. In other words, there is a trade-off relationship between the jitter peaking phenomenon and the pattern jitter of the oscillation control voltage signal V_CTR.
As mentioned above, the phase-locked loop is designed to output the PLL clock signal CLK_PLL with low jitter by filtering the jitter component. However, a preferred filtering operation cannot be achieved because of the jitter peaking phenomenon in the jitter transfer function of the phase-locked loop. Further, if the resistance value of the resistor R is adjusted in order to remove the jitter peaking phenomenon, the pattern jitter of the oscillation control voltage signal V_CTR is increased so that an exact phase/frequency locking operation cannot be achieved.